封装FET

 MwT-1789HL Application Note
 MwT-1789LN Application Note
 MwT-17Q3 Application Note

Model

Package

Gate

Gate

Gate

Chip

S.S. Gain

N. F.

Ga @

P-1dB

IP3

Nominal

Ideal

Available

Width /

Layout

Drain

Thick-

@12GHz

@12GHz

N.F

@

@

Chip

Circuit

Sealed /

Length

Method

Source

ness

Typ/Min

Typ/Max

@12GHz

12GHz

12GHz

Size

Hermetic

Bond Pads

& VIA Hole

Typ/Min

Typ/Min

Typ

New

um

Qty

mil, y/n

dB

dB

dB

dBm

dBm

um • um

MwT-1789HL *

sot89

2400/0.8

Interdigit

4, 4, 5

4, no

--

(3)

14.0 (1)

28.0

46

1130 • 279

High Linearity

MwT-1789LN *

sot89

2400/0.8

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